1. Field of the Invention
The present invention relates generally to memory interfaces responsive to an input data packet input from a data-driven type processor for accessing an image memory and outputting the result, and more specifically, to a memory interface responsive to an input data packet which has been output from a dynamic data driven type processor and attached with a generation number which is attached sequentially according to the order of input time for accessing the content of an image memory, for example, using the generation number as an address and outputting the result.
2. Description of the Related Art
In recent years, there have been rising demands for an increase in the operating speed of a processor, for example in the field of image processing. Parallel processing has attracted much attention as one measure for increasing the speed of a processor. Among various architectures suitable for parallel processing, an architecture called data-driven type is especially noticeable.
In a data-driven type processor, processing proceeds based on a simple principle that "a certain processing is performed when all the necessary input data is collected and resources such as operation units necessary for the processing are secured". One of the things technically required for implementing this architecture is a mechanism for detecting when all the necessary input data is collected (firing). An architecture type permitting input of only one set of data for a certain processing when the firing is detected is called a static data driven type, while an architecture permitting input of two or more sets of data is called a dynamic data-driven type.
The static data driven type can not sufficiently cope with the processing of time series data such as a video signal, and therefore it is necessary to employ a dynamic architecture for such data. In this case, since there are a number of input sets for a certain processing, a concept of generation identifiers for identifying these plurality of input sets, for example, should be introduced. Herein, such generation identifiers will be referred to as generation numbers.
One example of such a data-driven type information processing device suitable for image processing is presented in an article titled "An Evaluation of Parallel Processing in the Dynamic Data Driven Process" (Japanese Society of Information Processing Engineers of Japan, Microcomputer Architecture Symposium, Nov. 12, 1991). FIG. 1 is a block diagram showing a data-driven type information processing device suitable for image processing, utilizing a conventional memory interface. Referring to FIG. 1, the data-driven type information processing device includes a data-driven type processor 1 for image processing, an image memory 3, and a conventional memory interface 24.
Input data packets having generation numbers attached according to the order of input time are input in a time-series manner through data transmission paths 7 and 8. Data-driven type processor 1 applies an access (reference to/updating of the content of image memory 3, for example) demand via image memory 3 to memory interface 24 based on a preset processing content through a data transmission path 4. Memory interface 24 accesses an address in image memory 3 corresponding to the address (generation number) included in the input data packet through a memory access control line 6 in response to the access demand, and returns the result to data-driven type processor 1 through a data transmission path 5. Data-driven type processor 1 performs a processing to the input data packet in response to the output of memory interface 24 and outputs an output a data packet through a data transmission path 9 or 10.
FIG. 2 illustrates one example of the field structure of such an input data packet input to memory interface 24 through data transmission path 4. Referring to FIG. 2, the input data packet includes an instruction code 26, a generation number 28, first data 30 and second data 32.
Instruction code 26 represents the content of a processing to the image memory. The content of the processing includes, for example, referring to or updating of the content of image memory 3.
The generation number 28 is an identifier attached to the input data packet applied to data-driven type processor 1 through data transmission path 7 or 8 according to the order of input time series. Data-driven type processor 1 utilizes the generation number for matching at the time of data waiting. Meanwhile, for memory interface 24, the generation number has the same meaning as the address to image memory 3. More specifically, memory interface 24 accesses a corresponding address in image memory 3 based on the generation number.
The first and second data 30 and 32 are interpreted differently according to the content of instruction code 26. For example, if the instruction code 26 represents updating of image memory 3, the first data 30 is data to be written to the image memory and the second data 32 is not utilized and thus is meaningless. When the instruction code 26 represents reference to image memory 3, the first and second data 30 and 32 are both not utilized and thus are meaningless.
In the input data packet shown in FIG. 2, the instruction code 26 is of 8 bits, the generation number 28 is of 24 bits, the first data 30 is of 12 bits, and the second data 32 is also of 12 bits.
Referring to FIG. 3, the field structure of an output data packet output from memory interface 24 through data transmission path 5 is as follows. The output data packet includes an instruction code 34, a generation number 36, and data 38.
For the instruction code 34 of 8 bits and the generation number 36 of 24 bits, the instruction code 26 and the generation number 28 of the input data packet to memory interface 24 shown in FIG. 2 are output as they are. As for the data 38, the result of accessing to image memory 3 is stored. The data 38 is of 12 bits.
FIG. 4 illustrates the structure of the generation number 28 in detail. Referring to FIG. 4, the generation number 28 includes a 3 bit field address FD#, an 11 bit line address LN#, and a 10 bit pixel address PX#.
The generation number 28 shown in FIG. 4 corresponds to the logical configuration of image memory 3 as shown in FIG. 5. The logical configuration of image memory 3 shown in FIG. 5 includes eight field image memories 40a-40h specified by the 3 bit field address FD#. Each field image memory includes 2.sup.11 =2048 lines in the vertical direction corresponding to the 11 bit line address LN# shown in FIG. 4. Each of the lines includes 2.sup.10 =1024 pixels corresponding to the 10 bit pixel address PX# shown in FIG. 4.
A signal input packet has already been attached with a generation number according to the order of input time series when it is input to data-driven type processor for image processing 1 (see FIG. 1). If an address for accessing image memory 3 is decided based on the generation number, the point of accessing moves scanning the memory in the horizontal direction starting from a point in the upper left of the first image memory 40a. When scanning for 1 line is completed, the point of access moves to the left end of the line immediately after that line. When scanning is completed as far as a point in the lower right of the first image memory 40a, the point of accessing moves to a point in the upper left part of the second image memory 40b. Hereinafter the point of accessing moves sequentially scanning image memories 40b-40h. When scanning is completed as far as a point in the lower right part of the last image memory, the eighth image memory 40h in this example, the point of accessing returns to a point in the upper left part of the first image memory 40a, and the same operation is repeated thereafter.
Since the memory interface moves the address for accessing the image memory according to the order of input of signal input packets to the data-driven type processor depending upon its purpose, the content of image memory 3 can be processed following scanning of a video image. This is why the memory interface is suitable for video image processing.
Having such a structure, however, the interface suffers from a disadvantage in that it can not designate an arbitrary address and read out its content. This is because such a conventional memory interface depends on the generation number of an input data packet for an address for accessing an image memory. Thus, a table conversion processing, in which a corresponding content in a table previously written in part of an image memory is read out based on the data value of an input data packet, can not be performed in a conventional memory interface.
Furthermore, often in video signal processing, some operation is performed referring to the content of adjacent regions, such as a mask processing in a 3.times.3 nearby regions, and the result is written in the same field or a different field. However, in a conventional memory interface, an address for accessing an image memory is decided exclusively by the generation number of an input data packet. Accordingly, any processing can not readily be performed referring to the content of an adjacent region as such. This applies to the case in which a processing, such as the above-described mask processing, is performed to the vicinity of an arbitrary pixel.